I'm going to discuss about the advances in physical design for next generation with FinFET and GAA technologies. GAA means gate all around technology. These both FinFET and gate around technologies are advanced CMOS technologies. CMOS means Complementary Metal Oxide Semiconductor. So with this FinFET and GA for the advanced nodes, it is helping improve the leakage power and the frequency and the area of the chip designs. So I'm going to discuss these ones in the coming slides. This is the FinFET like it has the substrate, source and drain. are connected with the gate. Gate has the control of the channel between the source and drain. Basically source emits the electrons and drain will collect that and gate will control that majority of the carriers or like the electrons. So compared to the planar transistor, gate is better controllability of the channel here. Because of that. In advanced nodes till 28 nanometer, we were using like the pin fats. So it has like a better switching times and higher current density compared with the plan transistors. we call like the source and rain, the channel we call it as like fin. We can have like multiple fins under a gate. It'll improve the. the leakage power and the current driving capabilities. So as the technology is scaling, then we are like multiple things. So if you're coming to that GAA technologies, so GAA is adding like multiple planar transistors all together, but it can be stacked. in the diagram, you see the diagram, Deep learner transistor is the first one. It has, source and drain, and controlled by very limited controllability of the gate. Of the gate, it has the less controllability of the channel. The second one is the FinFET. Gate has the better controllability of the channel. And the gate around technology. It has the surrounded with, the channel is surrounded completely with the gate. So it has better controllability and, for the lower technology nodes, what are the issues we are facing with the planar transistors are mitigated with the pinfix and what are the issues we are facing with the pinfix are fixed with the gate around technology. Low end currently nodes we are using the gate around to improve the drive strength, leakage, to reduce the power and improve the enhance the performance. So evolution from FinFET to GA, the limitation from the planar transistors are addressed with FinFET technology and The FinFETs giving the better performance and scalability, for the chip design. what are the issues now with the FinFETs like not able to resolve for the advanced semiconductor technologies like 2nm, 3nm, 2nm, 3nm technologies. Those issues we are solving with the TAA. So this impact of the ties and requirements, with the GAA is they layout complexity. We have so many complex rules for the GA technology and also we have a lot of economic challenges they might pitch quite reduce, and we have to go with that one instead of strategies. To fix all the DRC issues and go with the multi cut VRS and fix the congestion issues And all of that power distribution is one of the other challenge Like we have to properly plan the power Before otherwise like we may end up with a lot of power in the design in the chip so proper planning of the power with the Less number of, like reducing the pitch and with, reducing the metal width. So properly, estimation is very much required for the power distribution and electrometration. So we have to adopt like advanced EDA tools. like machine learning integration should be there for the advanced EDA tools. to work on this GAA technologies. This AI powered tool software with the layout and the brick design shows much earlier, so they can help like the convergence and improve the quality of the results. In the GAA, we were having like multi pattern like metals and even the standard cell pins are having the multi pattern format. the tools, GAA tools should understand All of these multi pattern rules and enable to legalize like moving the standard cells and routing the middle layers, like corresponding multi patterns aware on that, otherwise like we may end up with a lot of shorts, DRCs, and even like the congestion may increase. So I'd want you to use should help on that. The three C is in support. This is like multiple, advanced tools should handle all of these ones, like we have to day interface effectively, for this, TDSC design support. design strategies for advanced nodes are like, standard cell optimization, like the customer standard cell leverage for GA capabilities, track height reduction, and, pin access optimization of key, focus areas for the standard cell optimization and clocked synthesis. We have to properly fix the latency and skew numbers. And also we can go with the multi point CTS for the clocked synthesis. For the advanced nodes and signaling, it is the one of the major challenges. With the GAA or advanced technology because of the nets are more dominated. So it will cause the signal integrity challenges. So we have to go with the shielding and the buffer insertion strategies to fix all these issues. DFM integration design for manufacturing Like the, whatever we are going to manufacture, we have to address all of that issues much easier like multi cut vias and like even the metal phase. All of that we should take care of right with the advanced technologies to better correlation between the design before and after the manufacturing. So if you compare the power performance and area numbers between the FinFET and GA, the power is 20 percent improved compared with the basic like the FinFET technologies on the advanced nodes and the performance is like 15 percent improved on the lower technology like low technology nodes. Area is also 30 percent improved compared with FinFET designs. So overall there is a better improvement with the GAA. So the challenges in high density chip design. There are like more challenges, like highly dense designs. Like the thermal management is the critical one. We have to use like advanced cooling solutions and thermal wire placement. IR drop, IR wire placement. before going for. on the placement and in the clock tree optimization, use the better VT combinations and also variability control. we have to use the POCV and EOCV, for process variations. Yield optimization is, one of the thing, like we have to properly optimize the yield to correlate after the manufacturing. we have to use the advanced design techniques like, multi, multi cut VRs and, multi, like the DFM rules and all of that. For high speed designs, we have to properly take care of the clock distribution. If, like the clock distribution is a crucial thing for the high speed designs, We have to properly plan the clock, like which clocks are, the main clocks, which are, like, derived clocks. We have to properly build the clock tree for that, and even, the, try for the first clocks, and not building the clock tree for the test clock. we have to properly distribute the clock. Otherwise, we may end up with a lot of power. power issues and a lot of area issues. If you are not properly estimate the clock distribution and also like we can't meet the performance of the design. So other thing is like signal integrity. If you are not properly fixing the signal integrity, we may end up with a lot of crosstalk issues and like noise issues. So we have to properly estimate before going for the Routing, go for higher metal routing and giving the proper NDR rules, non default rules to fix that signal integrity issues. And also the on chip communication, like efficient data movement within the chip, like we are using the CDIS and architecture for the automation. So feature directions are 3D integration in the physical design, like the, we have to stack the multiple dice with the different technologies. Thank you. So the EDA tool should chop out all of these ones and quantum computing, the physical design tools out of the quantum designs, but also able to optimize those ones and, fix those ones, the issues with the quantum designs. And also the advanced design, the analog and mixed signal integration will become the crucial. So the EDA tool should, mitigate these issues in the advanced with advanced technologies. Coming to the conclusions, in the GAA, we are continuously scaling the technology with the GAA and we are adopting like more AI driven methodologies to optimize the designs to correlate the design with the manufacture, manufacturing. and also we are heterogeneous integration, like we are integrating multiple dice on the same package. So this is the like, conclusion from the advanced nodes with the GKA. So thank you very much.